What the OCI MSA didn't solve for AI scaling

Earlier this spring, AMD, Broadcom, Meta, Microsoft, NVIDIA, and OpenAI formed the Optical Compute Interconnect Multi-Source Agreement (OCI MSA) to bring coherence to AI infrastructure and establish a specification for co-packaged optics (CPO) scale-up networks. The architecture they aligned on is a slow and wide non-return-to-zero (NRZ) modulation paired with wavelength-division multiplexing. OCI GEN1 supports four wavelengths at 50 Gbps per channel, delivering 200 Gbps per direction per fiber, and the roadmap scales to 1.6 Tbps per fiber per direction.

This consortium settled the architectural debate over the direction of networking in AI.

The specification defines the first step in the architecture, but leaves the harder question open: How bandwidth continues to scale, and what comes after four wavelengths. The roadmap calls for adding wavelengths on the same fiber infrastructure to grow bandwidth, but does not specify which manufacturing approach will deliver them.

The road to more wavelengths is the answer

First-movers have already settled this argument. The OCI MSA's founding members endorsed four wavelengths as the GEN1 starting point, Ayar Labs has been on the eight-to-16 wavelength path for years, and NVIDIA's published roadmap, "A Roadmap Toward Sub-1 pJ/b Optical Interconnect," models a 16-wavelength interconnect as the route to the energy targets the MSA aims at.

The decision to use slow-and-wide is an energy-per-bit argument. Low symbol rates and simple encoding go together: NRZ carries one bit per symbol, while PAM-4 carries two but requires roughly three times the optical power to hit the same bit-error rate (BER). NRZ holds BER low enough that forward error correction (FEC) stays light, latency remains tight and predictable, and the link stays within its energy budget. On the electrical side, SerDes power per bit at 50 GBaud is roughly one-third that at 100 GBaud.

That regime must be preserved as bandwidth scales, or it can be walked back. Wavelength multiplication keeps the link inside the slow-and-wide regime, whereas symbol-rate escalation walks the architecture back out of it. For readers who want the underlying physics, see "Why 'Optics When You Must' is Now."

The industry can now treat increasing wavelength count as settled and turn to the next problem: Manufacturing stable precision laser arrays in massive quantities.

Three eras of photonic integration

Photonic integration has evolved through three manufacturing eras. Each was driven by the same forces that drove every transition in the semiconductor industry: Lower cost, higher reliability, and industrial-volume scale.

The first was the discrete optical assembly era. Components were made separately from exotic materials, precisely aligned by hand, and packaged individually. Expanding system capabilities meant more components and more assembly steps, and every fiber attachment was a costly potential failure point. The cost curve was flat by construction, or even negative, as yields fell.

The second era was silicon photonics. Components, including modulators, waveguides, and photodetectors, moved onto a single monolithic wafer, so a portion of the photonic stack could achieve the cost curves of the semiconductor process. Instead of scaling with assembly capacity, the silicon portion could scale by running more wafers on a single flow. The breakthrough was real but incomplete, because critical components could not be integrated. The stubborn, non-silicon III-V gain material was the holdout, and the cost curve remained partial: A high-volume foundry process bolted to a discrete-component bottleneck at the most demanding interface. The foundry flow excluded lasers, semiconductor optical amplifiers (SOA), and high-speed modulators.

The third era, heterogeneous integration of all photonic materials on a single wafer, has finally arrived. Combining III-V gain material with silicon photonics brings lasers, semiconductor optical amplifiers, and high-speed modulators into a single wafer-level process. The complete photonics signal chain consolidates on the wafer, and the gain material becomes just another step in a wafer process-flow cost curve, with wafer-level cost, scale, and reliability.

The trend towards ever-increasing integration is inevitable. It is the manufacturing transition CMOS underwent in electronics: A single, elegant process that absorbed new device types, compounded over generations at massive scale, and became the foundation for the modern semiconductor industry. Photonics is repeating it, just in time for the massive deployment in AI datacenters.

The wavelength staircase

The OCI GEN1 specification is four wavelengths at 50 Gbps NRZ, delivering 200 Gbps per fiber in each direction, with MSA channel spacing of 400 GHz. It serves as a practical starting point: Sufficient to demonstrate the architecture in production silicon and coordinate the supply chain, but not enough to support the next generation of GPUs, which will require higher bandwidth per fiber. OCI GEN1 sets the first minimum multi-wavelength standard, not the maximum.

Each step up the staircase runs slow and wide, so the per-channel electronics do not change. The dense wavelength-division multiplexing (DWDM) step occurs at wavelengths of eight or more, where channel spacing tightens. System-level bandwidth scales with the number of wavelengths: More lanes, more rings, no change in per-channel design effort. Doubling the wavelengths doubles the bandwidth without doubling the design cost. Eight wavelengths deliver 400 Gbps per fiber per direction, and 16 deliver 800. Bidirectional transmission over the same fiber further reduces the fiber count, and none of it requires faster SerDes, deeper FEC, or PAM-4 power and latency penalties.

Wavelengths bend the cost curve for per-fiber bandwidth and enable scale-up domains to grow from tens of GPUs today to thousands tomorrow. Multiplexing at the laser source prevents fiber-count growth, so the number of fibers per connector doesn't explode as the wavelength count rises.

The bigger payoff is what cluster size unlocks, rather than raw throughput. Larger, flatter, low-latency scale-up domains enlarge working memory, extend the context window, and add transformer layers, which together support deeper reasoning, fewer network stalls, and higher GPU utilization. Today's wavelength-count decision sets the ceiling on which models the resulting cluster can run in 2028 and beyond.

That gives system architects a sixth metric alongside energy per bit, latency, per-fiber throughput, and reach: Wavelength-scaling headroom on the same manufacturing flow. The question to ask is whether the supplier's light-source architecture extends to eight, 16, and beyond without re-engineering. Where the answer is no, the redesign is already on the calendar, with a two-year delta baked in.

Manufacturing decides the curve

The OCI MSA roadmap to 1.6 Tbps per direction per fiber is achievable on paper. The harder question is which manufacturing approach gets the industry there.

Discrete-laser supply chains were not built for hyperscale volumes, and the two structural paths hit the same wall by different routes.

The shared-laser path combines multiple lasers through a combiner-and-splitter network to feed a multi-wavelength source. Splitting losses scale with channel count: Every additional output tapped off the network costs the laser optical power it has to make up at the input. Each laser pushes harder to maintain budget across more channels, drive currents climb, and reliability margins erode at every wavelength step. The economics that work at four wavelengths do not extend to eight, let alone 16.

The dedicated-laser path uses one laser per wavelength, and assembly complexity scales linearly with channel count when multiplexing with discrete optics. A single module supplying 16 wavelengths across eight fibers would result in roughly 128 lasers, 128 fiber alignments, and 128 monitoring photodiodes. Each alignment has to hold to micrometre tolerances across temperature swings, package stress, and years of field life, and failure-rate math compounds at every interface.

Volume is the binding constraint. Hyperscale CPO will need millions of laser-source units per month, not tens of thousands, and discrete-laser approaches do not extend to those volumes regardless of which path is taken. This, rather than the architectural debate, is what has held DWDM back as a deployable architecture. The architectural debate was always going to settle here; the supply chain was not.

Once the next wavelength is no longer a discrete-component assembly step but becomes another circuit element on the silicon photonics wafer, the cost of adding wavelengths follows a semiconductor learning curve. Heterogeneous integration provides that curve, and the OCI roadmap requires it.

The CMOs of photonics

Heterogeneous integration is the manufacturing pattern that closes the integration gap silicon photonics has carried since its inception. III-V gain materials, modulators, photodetectors, and waveguides come together in a single wafer-level flow.

This is what CMOS did for electronics. CMOS established a single industrial process that absorbed transistor types, then logic, then memory, and eventually larger functional families, all within the same foundry flow. Each new device family inherited the process's cost curve rather than starting its own, and that inheritance is what lets CMOS compound over generations: Every advance in the underlying process improves every device built on it. The free ride came from the manufacturing pattern, not from the transistor.

SHIP™, Scintil Heterogeneous Integrated Photonics, is the equivalent pattern for photonic device integration. The claim is pattern equivalence, not scale equivalence: Photonics is repeating CMOS as a manufacturing transition, not as a market size.

The pattern is already running. SHIP™ sits on Tower Semiconductor's silicon photonics platform on 200 mm production lines today, the same lines that turn out tens of millions of pluggable optical transceivers. The 300 mm path is next.

The platform is already reaching beyond the laser source. At OFC 2026, four architecturally distinct system vendors independently requested SHIP™ extensions, each pursuing a different system goal: Deeper transceiver integration, advanced optical switching, high-speed modulation at scale, and integrated amplification architectures. Each needed the same underlying capability: III-V integration into the silicon photonics flow, for optical amplifiers and high-speed modulators that pure silicon cannot deliver. None of them was solving the same problem, and the common factor was the manufacturing pattern, not the device.

What comes after the first generation

Two generations from now, the scale-up fabric is a multi-rack signal chain that binds thousands of GPUs into a single coherent compute domain. The fiber plant that carried four wavelengths also carries 16, then the next, without rework. Lasers, modulators, photodetectors, and optical amplifiers are circuit elements on the silicon photonics wafer, not parts assembled into modules. The interconnect ceases to be an assembly problem and becomes a process-node problem. Power per bit decreases as the signal chain no longer crosses fiber interfaces and material boundaries, and bandwidth at the package edge rises with integration density.

The teams designing for that architecture today will hold the architectural position when it becomes the default. The teams that defer the manufacturing question will spend two generations rebuilding programs around suppliers who solved it earlier.

LEAF Light™ is the production proof: A single-chip DWDM-native light engine, demonstrated in eight- and 16-wavelength configurations compatible with microring-based CPO transceivers and manufactured on established production lines. Scintil's Series B included participation from NVIDIA as part of broader ecosystem alignment.

The OCI MSA settled the architecture. The path to ship it runs through heterogeneous integration.

Matt Crowley is the CEO of Scintil Photonics.

Contributed by OmniScale Media.